Abstract
The current technology allows the integration on a single die of complex systems-on-chip (SoCs) that are composed of manufactured blocks (IPs), interconnected through specialized networks on chip (NoCs). IPs have usually been validated by diverse techniques (simulation, test, formal verification) and the key problem remains the validation of the communication infrastructure. This paper addresses the formal verification of NoCs by means of a mechanized proof tool, the ACL2 theorem prover. A metamodel for NoCs has been developed and implemented in ACL2. This metamodel satisfies a generic correctness statement. Its verification for a particular NoC instance is reduced to discharging a set of proof obligations for each one of the NoC constituents. The methodology is demonstrated on a realistic and state-of-the-art design, the Spidergon network from STMicroelectronics.
Highlights
Up-to-date systems-on-chip (SoCs) are built by assembling modules such as processor cores, memories, and specialized Intellectual Property (IP) blocks
The current technology allows the integration on a single die of complex systems-on-chip (SoCs) that are composed of manufactured blocks (IPs), interconnected through specialized networks on chip (NoCs)
IPs have usually been validated by diverse techniques and the key problem remains the validation of the communication infrastructure
Summary
Up-to-date systems-on-chip (SoCs) are built by assembling modules such as processor cores, memories, and specialized Intellectual Property (IP) blocks. Our utmost objective is to provide a formal foundation to the verification of on-chip communication architectures, spanning from their initial design specifications to their RTL implementation. As a first step toward this objective, we proposed the generic network on chip model (GeNoC) [7, 8] It consists of a metamodel of on-chip communication architectures and its implementation in the logic of a theorem proving system. The metamodel detailed in this paper represents the transmission of messages on a generic communication architecture, with an arbitrary network characterization (topology and node interfaces), routing algorithm, and switching technique. The global correctness of the network model is preserved for all particular definitions satisfying the constraints It follows that, for any instance of a network, that is, for any T0, I0, R0, and S0, the property ℘(GeNoC(T0, I0, R0, S0)) holds provided that P1(T0), P2(I0), P3(R0), and P4(S0) are satisfied. This verification methodology is illustrated hereinafter on a realistic and state-of-the-art NoC, the Spidergon from STMicroelectronics [10]. ( The ACL2 scripts of our model and its instantiation for Spidergon are available at http://tima.imag.fr/vds/GeNoC/genoc.html. )
Sign-in/Register to view highlights & summary Sign-in/Register to access full text options 
Free) 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a call
