Abstract
Many multimedia applications require a flexible image pr ocessing architecture. In this paper, we present the use of a hardware acceleration module (Discrete Cosine Transform (DCT) and Inverse DCT (IDCT) coupled with a software partition running on a PowerPC Processor of a Xilinx FPGA. Therefore we have the benefits of flexible software partition on the PowerPC and the acceleration given by the remaining logic of the same FPGA. This implementation can be used in the context of video coding, object recognition, etc. The experimental results show optimization in processing time offered by hardware acceleration vs. software implementation.
Highlights
Most of video and image compression algorithms require high-speed video data processing capabilities in real-time, on-line applications such as digital video broadcasting and recording
The Memec Virtex II Pro (P7-FF672) Development Kit [12] provides a complete development platform for designing and verifying applications based on the Xilinx Virtex-II Pro FPGA family
The 2-D DCT and 2-D IDCT architectures were synthesized into a Xilinx Virtex 2 Pro family FPGA [13]
Summary
Most of video and image compression algorithms require high-speed video data processing capabilities in real-time, on-line applications such as digital video broadcasting and recording. The principal idea is tasks partitionng, a material block and a software block, carrying out same function as a pure software block This partitioning enables us to have an optimized circuit, on silicon area and processing time. The implementation of our system will be carried out using XPS tool (Xilinx Platform Studio) provided by EDK environment (Embedded Development Kits) [3] as well as the Core Generator tools included in ISE (integrated software environment) [4], to profit from an IP Xilinx DCT [5] respecting time to market constraint.
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