Abstract
Nonvolatile processor (NVP) attracts more and more attentions for its immunity to power loss in energy harvesting scenarios. The overall performance of an NVP is determined by its sleep and wake-up speeds, which refer to how fast the NVP can turn itself off and on when a sudden power failure occurs. To the best of our knowledge, this paper is the first work to improve the system-level sleep/wake-up speed of an energy harvesting NVP. A hybrid CMOS/ferroelectric nonvolatile flipflop (nvFF) and a high-speed voltage detector are designed and integrated in the proposed NVP to jointly minimize its sleep and wake-up time. Measurement results demonstrate 46 μs wake-up time and 14 μs sleep time, which is up to 18 and 24 times speedup over existing works. This approach not only improves the robustness of the NVP to power fluctuations but also brings significant advantages for better utilization of harvested energy.
Published Version
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