A fault tolerant control approach for a three-stage cascaded multilevel solid state transformer

Abstract

A solid state transformer (SST) is going to be a vital part of the future grid due to its attractive features such as step-up/step-down of grid voltage, provision for an intermediate DC bus to interface renewable energy source and energy storage, controlled bidirectional power flow between two girds etc. Even though the reliability of the SST is questioned due to high switching device count, redundant modules can be integrated into the SST architecture to ensure uninterrupted operation. Unlike the high short circuit current withstanding capability of the passive copper windings in a conventional iron-and-copper based transformer, an SST can fail in the event of any fault due to the limited over current rating of the switching devices. Several fault identification and isolation techniques for the power converters have been researched, but the power converter operation during the time frame between fault isolation and post fault restoration was neglected. In this paper, the grid current and sub-module capacitor voltage deviations are analysed during the time frame between fault isolation and post-fault restoration. A new control approach is proposed to improve the fault tolerance of the SST by identifying a short circuit fault and limit the short circuit current before a healthy module is brought into operation i.e., post-fault restoration. In the proposed method, the control is designed to switch from the conventional control to a fault tolerant control scheme in the event of fault. The proposed control method is validated using the PLECS real time (RT) hardware-in-loop (HIL) platform and results are presented.