A faster approach to periodic data flipping of SRAM array for NBTI recovery

Abstract

Negative Bias Temperature Instability (NBTI) is a prime reliability issue for micro and nano-scale semi-conductor devices. Due to continuous device scaling, NBTI effect has become more severe than before and affected device life-time. Memory devices like SRAMs are tremendously affected by NBTI as the PMOS transistor gate is connected at `0' logic for a long time. Several device-level and architecture-level solutions have been proposed to improve device life-time by interrupting NBTI degradation. Such an architectural level solution is to flip data in a particular SRAM cell after a certain time, causing periodic stress and relaxation. SRAM data flipping techniques proposed so far are not so time friendly as it is needed to access each memory cell individually and flip the data stored. It makes the process more time consuming and inconvenient for present ultra-fast system with high activity factor. In this paper, we proposed a new 7-T SRAM cell to allow flipping data of more than one memory cells at same clock pulse, hence decreasing the flipping time of entire memory array and concluded that with the new proposed cell and flipping procedure, data flipping of the entire memory array will become much faster which will ensure convenient NBTI recovery.