Abstract
The transistor simulation tools (e.g. TCAD and SPICE) are widely used to simulate single event effects (SEE) in industry. However, due to the variances of the physical parameters in practical design, e.g. the nature of the particle, linear energy transfer and circuit characteristics would have a large impacts on the final simulation accuracy, which will significantly increase the complexity and cost in the workflow of the transistor level simulation for large scale circuits. Therefore, a new SEE simulation scheme is proposed to offer a fast and cost-efficient method to evaluate and compare the performance of large scale circuits in the effects of radiation particles. In this work, we have combined both the advantages of transistor and hardware description language (HDL) simulations, and proposed accurate SEE digital error models for high-speed error analysis in the large scale circuits. The experimental results show that the proposed scheme is able to handle SEE simulations for more than 40 different circuits with the sizes varied from 100 transistors to 100 k transistors.
Highlights
Radiation exists throughout the solar system, and includes Solar flares, Solar wind, Galactic cosmic radiation and radiation emitting from nuclear reactions [1]
When circuits are struck by particles, the effects of single event effects (SEE) might be different according to affected areas and circuit states
The probability of the occurrence of SEEs can be represented as follows: Pi where Npmos, i represents the number of the PMOS in unit i, Nnmos, i represents the number of the NMOS in unit i, Npmos represents the number of all PMOS in this complex circuit, Nnmos represents the number of all NMOS and λ represents the ratio of size of the PMOS and NMOS
Summary
Radiation exists throughout the solar system, and includes Solar flares, Solar wind, Galactic cosmic radiation and radiation emitting from nuclear reactions [1]. System level simulation is another method to rapidly evaluate the SEE mitigation performance of the circuits It carries out the error in jections in the data stream or memory units based on the SEU rates [13,14]. In order to resolve these issues, in this paper, we propose a new SEE simulation scheme to offer a fast and cost-efficient method to evaluate and compare the performance of large scale circuits. The gate components can be modified to adapt to different manufacturing processes, and the SEE spice model can be modified to adapt to different radiation envi ronments, as required In this way, the proposed scheme can make full use of existing models to build simulation environments and be adapted for various requirements.
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