Abstract

IR drop is a physical phenomena affecting timing and logical operation of the circuits. As technology nodes shrink this has become an unavoidable menace and this effect is pronounced at high clock frequencies. Excessive IR drop is responsible for path delay defects. We propose a frame-work which can predict IR drop for different operating modes of the design including test mode. Test pattern IR drop analysis is done late in the design cycle and is time and resource consuming. Evaluation of IR drop depends on multi physics effects and is time consuming and expensive. Industry EDA tools such as Redhawk, PrimeRail, Totem are used for IR drop analysis. These tools often perform exhaustive power grid analysis to identify critical IR drop regions and Engineering Change Order(ECO) is performed to fix these potential violating instances. We propose a light weight scalable machine learning model which can predict final post-ECO IR drop based on the features from pre-ECO design. Since the pre-ECO design is very early into the project phase our ML model avoids multiple iterations to predict final post- ECO IR drop thus saving time. We have implemented our machine learning model for medium scale industrial design A containing a million cell instances for typical typical (TT) corner at 0.945v. Early experiments on our industrial designs show coefficient of determination is 0.828 for the final IR drop prediction model. This model can save significant amount of time and cost while predicting the post- ECO design features and fixing the IR drop problem across functional and test mode.

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