A Fast-Lock Low-Jitter DLL with Double Edge Synchronization in 0.18µm CMOS Technology

Abstract

Aims : This paper describes a fast -lock, low-power, low-jitter and good duty -cycle correction capability delay locked loop with double edge synchronization which is mainly used in clock alignment process.A clock aligners task is to phase -align a chip internal clock with a reference clock. The main advantage of delay locked loop rather than phase locked loop is related to good jitter performance of it. Double edge synchronization method leads to more power consumption and it can increase rms and peak -to-peak jitter therefore, in this work rms jitter, peak -to-peak jitter and power consumption are implemented to