A 100 MHz-Reference, 10.3-to-11.1 GHz Quadrature PLL with 33.7-fsrms Jitter and -83.9 dBc Reference Spur Level using a -130.8 dBc/Hz Phase Noise at 1MHz offset Folded Series-Resonance VCO in 65nm CMOS

Abstract

State-of-the-art high-performance transceivers and data converters face the urgent need for clock jitter values in the range of a few tens of femtoseconds. To achieve such an ultra-low jitter characteristic, existing PLLs with sub-60fs RMS jitter require expensive and bulky external reference clocks with ultra-low jitter and high output frequency. For example, [1] presents a CMOS PLL with 51.7-fSms jitter and the adopted crystal oscillator frequency is as high as 500 MHz with $175 \mathrm{~mW}$ power consumption. When such PLLs are put into actual use, the overall cost of the high-quality reference based PLLs is considerably high. As an alternative, this paper presents a sub40fs RMS jitter PLL without the necessity of the demanding reference clock Fig.1 (top right). In this case, the key point lies in how to exchange power for the extremely superior performance of VCO. As shown in Fig.1 (bottom left), the phase noise(PN) of the multi-core oscillators can be scaled down by $10 \log (\mathrm{N})$ with N coupled oscillators [2]. However, the multi-core oscillator suffers from synchronization issues due to mismatch between each core, which limits further PN improvement, particularly considering large quantity of cores. Large silicon area is another major drawback [3]. The series resonance VCO adopting BiCMOS technology reported in [4] has the potential” to achieve ultra-low PN, as shown in Fig. 1 (bottom middle). However, the circuit topology might not be feasible for CMOS technology. A CMOS series-tank oscillator was reported in [5] but has not yet proved in silicon. This paper proposes a folded transformer-based series resonance CMOS VCO with quadrature output, as shown in Fig.1 (bottom right). It achieves -130.8dBc/Hz@1MHz measured phase noise from 10.6 GHz. Thanks to the proposed ultra-low phase noise VCO, a 10.3-to-11.1GHz PLL with $33.7 \mathrm{fs} m \mathrm{~ms}$ jitter and -83.9 dBc reference spur level is achieved. To the best knowledge of the authors, this work reported the lowest phase noise CMOS VCO at similar frequencies and the lowest jitter PLL adopting less than 200 MHz reference clock.