Abstract
Digital devices use decimal arithmetic in most of the application which make devices easy to use and feasible to human computation. BCD (Binary Coded Decimal) is very common in digital computational devices which display decimal numbers whereas binary is the number system that is recognized by machines. So, BCD is needed to make machine results human readable that is to be converted from binary number. In this work, a new algorithm is proposed to provide hardware support for binary to BCD conversion. This converter can be used for 2digit BCD number to be translated from a 7-bit binary number. The proposed circuit is 20.08% area-efficient and 33.49% delay efficient than the existing best known Shift Add by Constant Architecture. The proposed architecture works for all the general purpose of binary to BCD conversion whereas the existing best known converters are for specific multiplication purpose and are not feasible for generalized use. Hence, the proposed converter circuit is area and delay efficient with the large-scale and extensive applicability.
Published Version
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