A false-path aware formal static timing analyzer considering simultaneous input transitions

Abstract

Timing closure has always been the biggest bottleneck in the modern VLSI design flow. Traditional timing verification techniques such as Static Timing Analysis (STA) are usually too conservative or sometimes too optimistic. This inaccuracy may lead to an unnecessary procrastination of time to market or even silicon failure. It is mainly due to the inability to detect false paths and handle multiple-input-transitioning effects in the timing analysis process. In this paper, we proposed a novel Formal Static Timing Analysis (FSTA) technique which can model the multiple-input transitioning effects, detect the false paths, and generate an input transition pattern for the true critical path at the same time. This is achieved by tightly integrating a state-of-the-art Boolean Satisfiability (SAT) solver with a STA engine, under a specialized multiple-input-transition timing library. Our experiments compare the FSTA engine with the traditional STA and random simulation techniques. The results show that our approach greatly outperforms random simulation while obtaining more accurate timing analysis results than STA.