A fabrication process for a 580 ps 4 kbit Josephson non-destructive read-out RAM

Abstract

A 4-kb Josephson nondestructive readout (NDRO) random access memory (RAM) has been developed. A process for fabricating the 580-ps 4-kb Josephson NDRO RAM is described that is based primarily on the use of Nb/AlO/sub x//Nb technology and state-of-the-art planarization. The process has evolved from a 1-kb Josephson NDRO RAM previously reported, with changes in memory cell structure, multilevel construction, layer planarization, and minimum design rules. Advanced memory cells with two stacked superconducting loops on which control lines are prepared are formed on ground plane insulation layers. Eight-stacked layers are formed from 200 approximately 300-nm-thick Nb films and 200-nm-thick SiO/sub 2/ films for planarized four-level interconnections including resistors. Planarization is achieved mainly by means of an undercut etching-mask-use lift-off planarization (ULOP) process. A 6-mm-square chip containing more than 25000 junctions whose minimum size is 3 mu m square and top level lines as small as 1.5 mu m in width and space have been successfully fabricated.