A dynamic-threshold SOI device with a J-FET embedded source structure and a merged body-bias-control transistor. I. A J-FET embedded source structure properties

M Horiuchi

doi:10.1109/16.853035

A dynamic-threshold SOI device with a J-FET embedded source structure and a merged body-bias-control transistor. I. A J-FET embedded source structure properties

M Horiuchi

https://doi.org/10.1109/16.853035

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Journal: IEEE Transactions on Electron Devices	Publication Date: Jan 1, 2000
Citations: 8

Affiliation: Hitachi (Japan)

#Source-drain Breakdown Voltage #SOI CMOSFETs + Show 8 more

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Abstract

The floating-body effects in SOI CMOSFETs are fully suppressed by embedding a J-FET source structure immediately beneath the source/drain junction. The drain of the J-FET consists of a Schottky barrier diode; the holes generated in the body can easily be ejected into the source through the forward-biasing of this diode. The source-drain breakdown voltage and drain-induced barrier-lowering characteristics of this device are the same as those of a bulk device. With this structure, the body potential syncrhronously couples to the gate bias in the dynamic mode without potential hysteresis when the body-to-source resistance is properly designed. The inverter-chain delay time should be 45% of that of a bulk device operating at 1 V without an excess load.

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