A Dynamic Sampling Approach for Cost Reduction in Semiconductor Manufacturing

Abstract

In semiconductor manufacturing, metrology is generally a high cost, non-value added operation that impacts significantly on cycle time. As such, reducing wafer metrology continues to be a major target in semiconductor manufacturing efficiency initiatives. Data-driven spatial dynamic sampling methodologies are here compared. Such strategies aim at minimizing the number of sites that need to be measured across a wafer surface while maintaining an acceptable level of wafer profile reconstruction accuracy. The Spatial Dynamic Sampling approaches are based on analyzing historical metrology data to determine, from a set of candidate wafer sites, the minimum set of sites that need to be monitored in order to reconstruct the full wafer profile using statistical regression techniques. Spatial Dynamic sampling is then implemented in various strategies that guarantee coverage of all the possible sites in a given set of process iteration. In this way, the risk of not detecting previously unseen process behavior is mitigated. In this work, we demonstrate the efficacy of spatial dynamic sampling methodologies using both simulation studies and metrology data from a semiconductor manufacturing process.