Abstract
In semiconductor manufacturing, metrology is generally a high cost nonvalue-added operation that significantly impacts on cycle time. As such, reducing wafer metrology continues to be a major target in semiconductor manufacturing efficiency initiatives. A novel data-driven spatial dynamic sampling methodology is presented that minimizes the number of sites that need to be measured across a wafer surface while maintaining an acceptable level of wafer profile reconstruction accuracy. The methodology is based on analyzing historical metrology data using forward selection component analysis (FSCA) to determine, from a set of candidate wafer sites, the minimum set of sites that need to be monitored in order to reconstruct the full wafer profile using statistical regression techniques. Dynamic sampling is then implemented by clustering unmeasured sites in accordance with their similarity to the FSCA selected sites and temporally selecting a different sample from each cluster. In this way, the risk of not detecting previously unseen process behavior is mitigated. We demonstrate the efficacy of the proposed methodology using both simulation studies and metrology data from a semiconductor manufacturing process.
Highlights
M ETROLOGY is a critical activity in industry [21], [23] and, in particular in semiconductor manufacturing [13], [27], where it is increasingly becoming the focus of attention as feature sizes continue to shrink and wafer diameters increase from the current industrial standards of 200 mm and 300 mm to 450 mm [11]
The methodology is based on analysing historical metrology data using Forward Selection Component Analysis (FSCA) to determine, from a set of candidate wafer sites, the minimum set of sites that need to be monitored in order to reconstruct the full wafer profile using statistical regression techniques
In [15] we introduced a methodology for optimum wafer site selection for wafer sampling plan design based on Forward Selection Component Analysis (FSCA) [16]
Summary
M ETROLOGY is a critical activity in industry [21], [23] and, in particular in semiconductor manufacturing [13], [27], where it is increasingly becoming the focus of attention as feature sizes continue to shrink and wafer diameters increase from the current industrial standards of 200 mm and 300 mm to 450 mm [11]. In recent years there has been increasing interest in developing data driven wafer measurement plan optimization methodologies that can take account of spatial correlation to further reduce the number of sites that need to be measured. Vincent et al [25] developed a methodology based on Principal Component Analysis (PCA) modelling and minimum-variance estimation They considered both within wafer spatial patterns and temporal correlation patterns in their formulation, but concluded that only spatial patterns were present in the practical litho-etch process case study they used to validate their approach. We extend our previous work in [15] to address this concern by developing a novel dynamic spatial sampling methodology that improves wafer coverage temporally with minimal information loss in terms of the ability to reconstruct the full wafer profile with the optimally selected FSCA sites.
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