A Dual-Split-Controlled 4P2N 6T SRAM in Monolithic 3D-ICs With Enhanced Read Speed and Cell Stability for IoT Applications

Abstract

Recent monolithic 3-D integrated-circuit (3D-IC) technology tends to induce stronger driving capability in pMOS transistors, compared to that obtained using existing processes. Thus, conventional 6T SRAMs suffer degradation in access speed and write margin when used in monolithic 3D-ICs. This letter proposes a dual-split-controlled 4P2N (DSC-4P2N) SRAM with corresponding read and write assist schemes capable of providing a larger cell read current and higher write margins compared to 4N2P SRAMs implemented in monolithic 3D-ICs. The proposed DSC scheme improves $4.8\times $ in read stability compared to 4P2N SRAM without DSC. A fabricated DSC-4P2N SRAM in monolithic 3D-IC was shown to outperform the previous 6T SRAMs.