A dual-rail compact defect-tolerant multiplexer

Abstract

As the dimensions of CMOS devices scale down to the nanometers, manufacturing defects are becoming a challenging concern in current and future technologies. This work aims at improving defect tolerance in FPGAs which are certainly affected by technology downsizing. Since the cornerstone of the FPGA logic and interconnect resources is the multiplexer, we propose a defect-tolerant multiplexer architecture based on differential logic. This architecture proved to be more resilient to single defects (opens and bridges) than its single-ended standard counterpart and more compact than existing hardened architectures. The architectures were studied under single defect injection by a tool that models several possible defects for a given design according to its extracted netlist. The robustness gain using differential logic was assessed for different sizes of FPGA look-up tables. Eventually, three different aging phenomena resulting in device wear-out were examined. An aging-aware analysis was performed according to an appropriate simulation flow. Results were given for the proposed multiplexer architecture and its standard counterpart.