A Dual-Gate Complementary Metal-Oxide-Semiconductor Technology with Novel Self-Aligned Pocket Implantation which Takes Advantage of Elevated Source/Drain Configurations

Abstract

A dual-gate complementary metal-oxide-semiconductor technology with novel self-aligned pocket implantation is demonstrated which takes advantage of the elevated source/drain (S/D) configurations. Using the present procedure, S/D junction capacitance and leakage current were significantly suppressed for p-channel metal-oxide-semiconductor field-effect-transistors (MOSFETs) as well as for n-channel MOSFETs without degradation of the short channel characteristics. These results are interpreted in terms of the fact that the pocket impurity profiles shift to the upper positions in the deep S/D regions, though the impurity distribution at the gate edges was hardly varied. Furthermore, the suppression effects were more marked for a higher pocket implantation dosage, which will be required to suppress the short channel effects in future MOSFETs. In addition, improvement of drivability due to the reduction of the parasitic S/D resistance, an original benefit of the elevated S/D engineering, is maintained by the present technique. The present self-aligned pocket procedure is very promising as a key technology beyond the 0.1 µm node.