A dual complex pole-zero cancellation frequency compensation with gain-enhanced stage for three-stage amplifier

Abstract

A dual complex pole-zero cancellation (DCPC) frequency compensation technique with gain enhanced stage (GES) for three-stage amplifier is proposed in this paper. It uses one pair of complex zeros to cancel one pair of complex poles, resulting in feature that the frequency response of three-stage amplifier exhibits that of a single-pole system. Meanwhile, the effective transconductance of output stage can be greatly increased by several times which are equal to gain of GES, and the power dissipation can be decreased when a GES is introduced. Thus the gain-bandwidth (GBW) is expected to be increased about 10 times compared to the conventional nested miller compensation (NMC) approach. Moreover, this technique requires only one very small compensation capacitor even when driving a large load capacitor. A GBW of 1.23 MHz, DC gain of 111 dB, PM of 86° and power dissipation of 0.29 mW can be achieved for a load capacitor of 500 pF with a single Miller compensation capacitor of 14 pF at a ± 1 V supply in a standard 0.6-?m CMOS technology.