A double-node-upset completely tolerant CMOS latch design with extremely low cost for high-performance applications

Abstract

This paper presents a novel radiation hardened latch (namely DCTELC) that can completely tolerate single-node upsets and double-node upsets (DNUs) for high-performance applications. The latch mainly consists of a clock-gating based dual-interlocked-cell (DICE), a 2-input C-element, and a clock-gating based 2-input C-element. The latch introduces isolated nodes to tolerate DNUs and the isolated nodes have no time to float for high-performance applications. Simulation results demonstrate the complete DNU tolerance for the latch and an 86% power-area-delay product (PADP) saving on average compared with state-of-the-art DNU-tolerant latches. Moreover, compared with the existing latches of the same type, the power dissipation, silicon area, transmission delay, and PADP of the proposed latch are the smallest.