A Dislocation Formation Model of Trench‐Induced Dislocations in Dynamic Random Access Memories

Abstract

In the early development of 4 megabit dynamic random access memories (4M DRAMs) with deep trench design some of the trench capacitor memory cells showed high charge leakage. This electrical failure was attributed to the occurrence of dislocations in the close vicinity of the trenches which were therefore termed trench‐induced dislocations (TIDs). Process experiments revealed the stages and parameters influencing the TID formation and low‐dislocation wafers were then produced. Systematic transmission electron microscope (TEM) analysis was performed on the wafers from the production experiment wafers. The TIDs showed a remarkable sequence of development throughout the different stages. Specific parameters having a major effect on the initial nucleation and subsequent propagation were identified. The combined results from the processing experiments and subsequent TEM examinations enabled a consistent model to be evolved in which the dry trench etching and the following oxidation processes played key roles, but not the ion implantations.