A direct-write electron beam lithography process using multi-layer resists and its application to silicon-on-sapphire technology

Abstract

A negative tri-level resist process for the gate and interconnection layers of a CMOS Silicon-on-Sapphire (SOS) process has been established. Automatic chip-to-chip registration has been demonstrated using special marks etched into the epitaxial silicon layer. The resist processes chosen are of sufficient sensitivity to enable the exposure system to be operated near its maximum speed whilst maintaining the optimum resolution. Both interand intralayer e-beam/optical lithography mix and match processes have also been demonstrated.