A Digital Intensive Fractional-N PLL and All-Digital Self-Calibration Schemes

Abstract

A digital intensive PLL featuring a digital filter in parallel with an analog feed-forward path and a digital controlled oscillator (DCO) is presented. Digital loop filter replaces analog passive filter to reduce chip area and associated gate-leakage in advanced process. It also allows the PLL loop gain and DCO gain to be digitally calibrated to within 100 ppm within 50 mus. Such fine frequency resolution enables the PLL to accurately compensate for the loop parameter variation due to process, voltage and temperature (PVT). The analog feed-forward path is insensitive to quantization error of fractional-N divider and DCO nonlinearity. Direct modulating the DCO frequency and phase through the analog feed-forward path, and compensating the modulating signal digitally for the DCO gain variation are demonstrated. At 3.6 GHz all fractional spurs are under - 75 dBc. The phase noise at 400 kHz and 3 MHz are -115.6 dBc/Hz and -134.9 dBc/Hz, respectively. The chip is fabricated in a 0.13 mu m CMOS process, and occupies an active area of 0.85 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and draws 40 mA from a 1.5 V supply including all auxiliary circuitry.