A device life cycle analysis of the WSI associative string processor

Abstract

The paper presents a comprehensive life cycle model and analysis of the WSI Associative String Processor (WASP). The model simulates the manufacture, acceptance, and operational life of a hypothetical WASP device using discrete event simulation techniques. Manufacturing defects are modeled with the negative binomial distribution, and operational faults are modeled using an adaptation of the MIL-HDBK-217F VHSIC reliability model. A full description is given of the simulation procedures and fault tolerant structure representations used in the model. A hypothetical WASP device manufactured in poor conditions and subjected to harsh operational conditions is shown to support nearly 8000 associative processing elements (APE) after 100000 h (11.4 yr) of continuous simulated operation. A simple post-manufacture device selection procedure is demonstrated which improves this harvest figure to over 10000 APE's. A hypothetical WASP device manufactured in good conditions and subjected to mild operational conditions is shown to support an average of over 12500 APE's after 100000 h of continuous simulated operation, without device selection. An architectural parameter sensitivity analysis for the hypothetical device shows that the areas of circuit elements at the upper levels of the fault tolerance hierarchy have greater significance than those at the leaf level for both yield and reliability. A test coverage analysis demonstrates the need for a comprehensive testing strategy for WSI devices. >