A design-flow for high-level synthesis and resource estimation of reconfigurable architectures

Abstract

Field Programmable Gate Arrays (FPGAs), due to their programmability, have become a popular design choice for control and processing blocks of an embedded system. However, this flexibility makes them larger, slower and less power-efficient than Application Specific Integrated Circuits (ASICs) and hinders their use in low-area and low-power applications. On the other hand, ASICs have their inherent drawbacks like lack of programmability and inflexibility. The solution is reconfigurable architectures that have improved flexibility over ASICs and better resource utilization than FPGAs. However, designing a reconfigurable architecture is a daunting task in itself due to lack of high-level design-flow support. This paper proposes an automated design-flow for system-level synthesis and resource estimation for generic as well as custom reconfigurable architectures. The experimental results show that the generated reconfigurable architectures are 79% more area and 76% more power efficient than generic academic FPGA-based implementations.