A Design-Optimized Continuous-Time Delta–Sigma ADC for WLAN Applications

Abstract

A third-order continuous-time delta-sigma (DeltaSigma) analog-to-digital converter (ADC) is presented for the conversion of an input signal bandwidth of 10 MHz. Design optimization towards minimal power consumption is demonstrated for the high-speed low-power building blocks of the DeltaSigma modulator. From this point of view, it is shown that GmC integrators are preferred over RC integrators in the low-pass filter of the modulator because they show a better tradeoff between power, speed, and accuracy. A new single-bit quantizer topology is presented that incorporates a local feedback path that improves stability using a switched-voltage technique. Finally, a design methodology for the single-bit digital-to-analog converter (DAC) in the feedback loop is proposed, focusing on the impact of high sampling rates on the stability of the converter. The presented continuous-time ADC achieves a simulated dynamic range of 72 dB and a signal-to-noise-and-distortion-ratio of 66 dB in a 10-MHz signal bandwidth. Therefore, it can be applied for WLAN broadband communication. The power consumption of the DeltaSigma modulator is limited to 7.5 mW. The chip is designed in a 0.18-mum triple-well CMOS technology