A design of 50/150/200 kbps, low power FSK transceiver using phase-locked loop with programmable loop bandwidth and integrated SPDT for IEEE 802.15.4g application

Abstract

This paper presents a 50/150/200 kbps, low power transceiver with one-point modulation and integrated single pole double throw (SPDT) switch for IEEE 802.15.4g application. To ensure that the proposed low power transceiver can operate at a multi data rate, multi data-rate (50/150/200 kbps) frequency shift keying (FSK) modulation is implemented using a phase-locked loop (PLL) with a programmable loop bandwidth. The bandwidth switching scheme is combined with the programmable loop bandwidth to support the high data rate in the PLL of the transmitter. In the receiver, the SPDT switch is integrated to share the antenna and matching network between the transmitter and receiver, thus minimizing the system cost. Also the active-RC band pass filter with the programmable bandwidth is designed to support the data rates of 50, 150, and 200 kbps. The capacitors in each data rate are shared efficiently to minimize the die area. The FSK transmitter is implemented using 0.18 μm 1-poly 6-metal complementary metal-oxide semiconductor technology. The die area of the transceiver is 4.0 mm2. The power consumption of the transmitter and receiver are 54 and 25 mW, respectively, when the output power level of the transmitter is +10.17 dBm at 1.8 V supply voltage. The phase noise of the PLL output at 1.8462 GHz is ?118.13 dBc/Hz with a 1 MHz offset.