Abstract
A CMOS 12-bit pipeline analog to digital converter (ADC) is designed for improved speed, resolution and low power consumption. The design incorporates 12 stages of 1-bit ADC cascaded to form pipelined architecture, with each stage containing a sub-ADC with a new approach of threshold inverter quantizer (TIQ) which substitutes the resistor array implementation and a multiplying digital to analog converter (MDAC) for quantized approximation of input voltage. The residue voltage is amplified in gain stage by closed-loop differential amplifier to have appropriate quantized output at the next stage. The sampling frequency is 200 MHz in 180 nm technology, and speed is 100 MSps and power is 50 mW, 0.5 pJ/step with 12-bit resolution.
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