A Delay-Line DPWM Architecture With Compensation Module and Delay-Adjustable Unit Based on DLL

Abstract

Due to the increasing resolution, the duty cycle in digital pulsewidth modulation (DPWM) is affected by the variation of external clock frequency or temperature, and the time error becomes larger and larger, even reaches a few nanoseconds. The increment of the duty cycle will affect the regulation performance of the converter and the output of DPWM. In this article, a delay-line DPWM architecture with a compensation module and a delay-adjustable unit based on delay-locked loop is proposed. The delay-adjustable unit is realized by using a multiplexer and some delay paths with different delay times, which effectively reduces the influence of temperature or the frequency changes from the input clock. Furthermore, a time compensation method is used to reduce the error generated by the critical path delays. A 10-bit DPWM with 781-kHz switching frequency is achieved on A-7 (xc7a100tfgg484) Xilinx FPGA, and the time error of the architecture decreases to around 500 ps. The duty cycle range is from 1.63% to 98.44%.