A delay model of CML gates valid under high-current effects

Abstract

In this paper a delay model of bipolar CML gates which extends that in [M. Alioto, G. Palumbo] for a wide range of bias currents is proposed. In particular, it accounts for high-current effects, i.e. the degradation in the transit time. The model proposed is derived from an approximate circuit analysis and has a simple compact expression as a function of the bias current, that makes it suitable for fast timing analysis or automatic bias current optimization. Simulation of CML circuits with a 20-GHz bipolar process shows that the model has a good accuracy in a wide range of current and loading conditions.