A DC-to-1-GHz Continuously Tunable Bandpass ADC

Abstract

This paper proposes a dc-to-1-GHz continuously tunable bandpass (BP) analog-to-digital converter (ADC). The tunability is realized by modifying the pipelined ADC-based $f_{S}/4$ BP-ADC. A passive switched capacitor-based error-delaying circuitry is used to delay the quantization noise generated by a pipelined ADC by programmable number of cycles to realize various noise transfer functions and a continuum of notches that cover dc to 1 GHz. A prototype was designed and simulated in Global Foundry 55-nm LP CMOS process. It achieves signal-to-noise ratio in excess of 80 dB in 15.625-MHz bandwidth while sampling at 500 MHz. The proposed architecture uses subsampling and aliasing to quantize signals from 54 to 890 MHz, which covers the over-the-air broadcast channels for North American Television system.