Abstract
Power problem has been one of most restricting the development barriers of processor. With enhancing of computer performance, there must be large cache to hide memory latency. Large cache can be consisted on one chip based eDRAM which has high density. Unfortunately, eDRAM must be refreshed frequently to maintain data, which would increase cache power. The paper aims at refresh problem of eDRAM, and put forwards a data drivered refresh with multi-bit error-correcting power optimize method. The experimental results show that the method which we put forward can greatly reduce the refresh power of eDRAM.
Highlights
With the increasing of single chip’s transistor number and clock frequency, power density of chip raised following with the power Moore law
Some previous papers used hardware mechanisms to exploit retention time variations by refreshing different DRAM cells at different refresh rates[9,10]. Another promising approach to increase DRAM refresh times is the use of error-correcting codes(ECC) to dynamically detect and correct bits that fail[11]
We will evaluate the impact of our DDRMC method on eDRAM cache power
Summary
With the increasing of single chip’s transistor number and clock frequency, power density of chip raised following with the power Moore law. Embedded DRAM(eDRAM) memory density increases three to four times compared to SRAM[1]. Pfbit curve represents the probability of a retention failure in a single bit cell and pfCache curve represents the failure probability of a 128MB eDRAM cache for different refresh times[5]. The probability of data loss would increase with refresh frequency descending, but high refresh frequency would increase refresh power. Reduce refresh power of eDRAM is an important method to reduce the cache power. To reduce refresh power of eDRAM and enhance reliability of cache data, we put forwards a data drivered refresh with multi-bit error-correcting power optimize method DDRMC(Data Drivered Refresh with Multi-bit Error-Correcting). When data of sub-array is valid, refresh would be started, otherwise refresh would be stopped to reduce refresh power. Because cache tag array is very small, and would be regularity accessed, so we used traditional SRAM
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