A $D$ -Band CMOS Amplifier With a New Dual-Frequency Interstage Matching Technique

Abstract

A new interstage matching technique has been proposed and successfully applied to a ${D}$ -band amplifier in a 65-nm CMOS technology. The proposed technique is based on a simultaneous conjugate matching at the interstages of multistage amplifiers at two frequencies, resulting in an increased bandwidth. The six-stage amplifier designed based on this technique shows a peak gain of 13.8 dB at 113.7 GHz with a 3-dB bandwidth of 11.2 GHz (110.6–121.8 GHz) without balun loss compensation, while consuming a dc power of 40 mW. Measured noise figure shows a minimum value of 10.8 dB at 115 GHz. The output $P_{1\,\text {dB}}$ and the saturation output power $P_{\mathrm{ sat}}$ are −14 and −3 dBm, respectively. The circuit occupies an area of $1100 \times 550~\mu \text{m}^{2}$ .