A Current and Temperature Limiting System in a 7-nm Hexagon™ Compute Digital Signal Processor

Abstract

A Qualcomm® Hexagon™ compute digital signal processor (CDSP) enhances reliability by integrating a current and temperature limiting system to avoid circuit failures from operating at excessive current levels for a sustained duration or from thermal runaway. The current and temperature limiting system consists of on-die current and temperature sensors, a limits evaluation (LE) circuit, and a randomized pulse modulation (RPM) circuit to control the instruction-issue rate. After the on-die sensors detect current or temperature exceeding a target threshold, the RPM circuit precisely adjusts the instruction-issue rate to maximize the performance while operating below the current and temperature specifications. The RPM circuit adapts performance in approximately five CDSP clock cycles after accounting for the clock-domain-crossing synchronization overhead to satisfy the 1- $\mu \text{s}$ latency requirement for the entire limiting system. From silicon measurements in a 7-nm CDSP, the RPM instruction-issue control circuit enables a 0.4% performance resolution across a wide range of operation from 100% to 0.4%. In addition, the RPM circuit avoids thread starvation during multi-threaded execution to maintain the CDSP quality of service (QoS). In comparison to a clock control for a limiting system, the RPM instruction-issue control enables CDSP performance gains ranging from ~2% to ~50%, depending on the workload and adjustment level, while satisfying the current and temperature specifications.