A cryogenic phase locking loop system for a superconducting integrated receiver

Abstract

The authors present a new cryogenic device, an ultrawideband cryogenic phase locking loopsystem (CPLL). The CPLL was developed for phase locking of a flux-flow oscillator(FFO) in a superconducting integrated receiver (SIR) but can be used for anycryogenic terahertz oscillator. The key element of the CPLL is the cryogenic phasedetector (CPD), a recently proposed new superconducting element. The CPDis an innovative implementation of a superconductor–insulator–superconductortunnel junction. All components of the CPLL reside inside a cryostat at 4.2 K, withthe loop length of cables 50 cm and the total loop delay 4.5 ns. So small a delayresults in a CPLL synchronization bandwidth as wide as 40 MHz and allowsphase locking of more than 60% of the power emitted by the FFO, even for FFOlinewidths of about 11 MHz. This percentage of phase locked power is three timesthat achieved with conventional room temperature PLLs. Such an improvementenables reducing the FFO phase noise and extending the SIR operation range.