Abstract
This paper proposes a dynamic voltage and frequency scaling (DVFS) technique for off-chip buses in multicore processors with identical processing cores. The proposed technique captures application’s sensitivity to off-chip access latency and dynamically tunes power parameters of the off-chip bus accordingly. Full system simulation has been used to evaluate the proposed idea in two main types of multicore architectures; Type 1 consists of complex superscalar processor cores while Type 2 consists of simple scalar processors. Simulation results have shown that the proposed DVFS scheme has achieved better results in Type 1; it reduces total off-chip bus energy, improves off-chip bandwidth energy efficiency and has negligible effect on processor performance.
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