A cost-effective high-voltage p-channel MOSFET implemented in a standard twin-tub technology: integrated IGBT gate driver

Abstract

This paper discusses the optimization and fabrication of a high-voltage p-channel extended drain MOSFET (ED-pMOSFET) using standard low cost twin-tub CMOS technology for digital applications, with only one additional processing step. The ED-pMOSFET transistor has been optimized using 2D simulations considering both specific on-resistance and breakdown voltage. Extended drain ED-pMOSFET transistors with low specific on-resistance (active area) R/sub on/=6.0 m/spl Omega//spl middot/cm/sup 2/ (@Vg=-5 V) and V/sub BR/=36 V have been implemented demonstrating competitive performance values with other p-channel devices previously reported in more sophisticated technologies. The proposed device along with n-channel LDMOS high-voltage devices and the standard low-voltage CMOS devices constitute a full smart power CMOS technology that can reach breakdown voltages up to 50 V and currents up to 1 A. This paper also analyses the benefits of a full-bridge output stage on integrated IGBT gate drive circuits. This full-bridge topology allows obtaining positive and negative gate voltages using a single floating power supply. Short-circuit protections have been also integrated, implementing an original soft shutdown process after an IGBT short-circuit fault. The monolithic integration is performed with this high-voltage CMOS technology. The IGBT driver has been experimentally tested, producing /spl plusmn/15 V gate-to-emitter voltage, and supplying the current peaks required by the 600 V IGBT switching processes. The driver characteristic response times are adapted to work at high switching frequency (>25 kHz) with large capacitive loads (3.7 nF).