A Cost-effective and Energy-efficient Architecture for Die-stacked DRAM/NVM Memory Systems

Abstract

Traditional DRAM-based memory systems are facing two major scalability issues. First, the memory wall problem becomes a major performance bottleneck. Second, conventional memory systems consume increasing power as the capacity increases, which could be as much as 40% of the total system power. These issues hinder the scaling of DRAM-based memory systems. Fortunately, emerging memory technologies, such as high bandwidth memory (HBM) and phase change memory (PCM), have the potential to solve these scalability issues. However, there is no single memory technology that can overcome these issues together. Therefore, a hybrid memory system could be a promising way to build a high-performance, large-capacity, and energy-efficient memory system. To achieve this goal, we propose a cost-effective and energy-efficient architecture for HBM/PCM memory systems, called Dual Role HBM (DR-HBM). In DR-HBM, the HBM plays two roles and is divided into two parts. A small portion of which, called HBM cache, is used as a cache for the PCM. The remaining HBM is used as a part of main memory. Furthermore, the HBM cache is also used to track page hotness without additional hardware support. Hot pages will be migrated to HBM when they are evicted from the HBM cache. The experimental results show DR-HBM outperforms two state-of-the-art hybrid memory systems, CAMEO [1] and RaPP [2]. Compared to the baseline in which both HBM and PCM are architected as a part of main memory without page migration, DR-HBM improves the performance by 63% on average.