Abstract
The state of the art video standard H.264/AVC is very popular worldwide for its efficient coding techniques. But recently the ITU-T Video Coding Experts Group (VCEG) and ISO/IEC Moving Picture Expert Group (MPEG) have been jointly developing the next generation video standard, called High Efficiency Video Coding (HEVC) which is expected to be more efficient in coding video. In this paper, we present a shared architecture which can compute the 8×8 Inverse Discrete Cosine Transform (IDCT) of the HEVC from that of the H.264/AVC using a new mapping technique. The hardware share approach ensures the maximum circuits reuse during the computation. The architecture is designed with only adders and shifters to reduce the hardware cost significantly. The design is implemented on FPGA and later synthesized in CMOS 0.18um technology. The results show that the proposed design has the maximum decoding capability of 67fps for 1080p full HD video.
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