Abstract

A correlation study of middle-of-line (MOL) electrical test method with its inline polysilicon gate (PC) and the diffusion contacts (CA) photolithography overlay data is presented in this paper for wafers fabricated by gate first CMOS process at 32nm. The physical analysis by scanning electron microscopy (SEM) further confirmed the accuracy of the electrical test method in explaining the physical values of global shift and local shift. Therefore, this electrical PC-to-CA testing methodology can be adopted cost effectively for an accurate MOL reliability assessment and process diagnostics in a timely and comprehensive manner.

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