A coordinated approach to partitioning and test pattern generation for pseudoexhaustive testing

Abstract

In this work, we propose a circuit partitioning and test pattern generation algorithm for built-in pseudoexhaustive self-testing of VLSI circuits. The circuit partitioning process is to partition a given circuit into a set of subcircuits such that pseudoexhaustive self-testing will be possible, while the test pattern generation process is to generate the pseudoexhaustive test patterns for each subcircuit using a linear feedback shift register (LFSR). Both problems are considered and solved in the same phase and lead to an efficient and well-coordinated solution. Experiments using computer simulation have been conducted. The results demonstrate that the proposed method is very good, especially for circuits that are highly locally connected.