A Programmable and Parameterisable Reseeding Linear Feedback Shift Register

Abstract

In this paper, we will design and implement a programmable and parameterizable Linear Feedback Shift Register (LFSR) for VLSI IC testing. The LFSR is used in circuit tests for test pattern generation (for exhaustive, pseudo-random, or pseudo-exhaustive testing) and as well as used for signature analysis. The complexity and size of SoCs are increasing at an alarming rate in modern times. There are errors that can occur during field manipulation of the device, attracting Logic Built In Self-Test (LBIST) over traditional ATE-based chip tests. A programmable and parameterizable LFSR can be used as test pattern generator for LBIST applications. The proposed design can generate any range of bits of vectors as per the choice of application. Also, the feedback polynomial can be parameterized to generate different length sequences. And LFSR can be configured into three different structural styles such as Fibonacci, Galois and Complete models. A Reseeding technique is introduced to leverage the LFSR to generate higher number of sequences without luring the storage requirements but testing out most of the random pattern resistant faults present in the circuit. The design is verified and analyzed in Xilinx Vivado suite