A contribution to the design of plastic packages for high voltage power integrated circuits

Abstract

The paper illustrates a research activity performed to investigate the problems associated with the electrical design aspects of plastic packages for high voltage PIC's. A preliminary study led us to subdivide the relevant problems into two groups: (a) problems connected with electrical stresses acting outside the package and on its external surface, which are of particular relevance in case of severe environmental conditions during the package's service; (b) problems associated with the electrical stresses acting inside the package. Reference design specifications for a particular high voltage PIC package were assumed for this work. The experimental tests performed on (purposely realized) test patterns proved that the first type of design problems can be satisfactorily addressed, by a proper implementation of existing IEC standards, to establish the minimum safe inter-lead distance. The second type of design problems requires a direct experimental approach. Specially designed test patterns have been subjected to several short and long term electrical tests. The relevant results show that, in this specific case, the package encapsulant resin can meet the electrical design goal, provided that the included silicon oxide (and its interface with the resin) is able to withstand the electrical stresses associated with the design constraints. >