A Concurrent Testing Scheme for Muller Circuits Using Reduced Ordered Binary Decision Diagram

Abstract

With the advancement of fabrication technologies in design of Integrated Circuits (ICs), faults that develop during the normal operation of the circuits becomes more prominent day by day. Such faults are not possible to detect by off-line test strategies, thus, the concurrent test or on-line test is becoming an important part in Design for Testability (DFT). Designing of concurrent testing schemes for asynchronous circuits is one of the challenging tasks in VLSI testing because of absence of global clock. It has been found that the number of existing concurrent testing schemes for asynchronous circuits is very few. These existing schemes have some drawbacks such as high area overhead, depends on the design protocol, issues of flexibility and scalability. In this work, we propose a concurrent testing scheme for asynchronous circuits, typically for the muller circuits, which follows the working principle of partial replication technique. The proposed scheme can handle all muller circuits irrespective of their design protocols and attains relatively low area overhead. Finally, the scheme uses Reduced Ordered Binary Decision Diagram (ROBDD), which improves the scalability of the scheme to handle large size circuits.