Abstract
A physics-based modeling framework is proposed to calculate the threshold voltage shift ( $\Delta \text{V}_{\mathrm {T}})$ in planar high-k metal gate (HKMG) n-MOSFETs for positive bias temperature instability (PBTI). Overall $\Delta \text{V}_{\mathrm { {T}}}$ is estimated using the uncorrelated contributions from the trap generation (TG) and the electron trapping subcomponents. The time evolution of $\Delta \text{V}_{\mathrm { {T}}}$ , measured using an ultrafast measure-stress-measure method during dc and ac stress and after dc stress, is predicted for different experimental conditions. The modeled TG component is verified by independent direct-current I–V method. The proposed model explains PBTI in differently processed HKMG gate stacks.
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