A Comprehensive Characterization Method for Lateral Profiling of Interface Traps and Trapped Charges in P-SONOS Cell Devices

Abstract

A comprehensive characterization method has been developed in this paper for reliable lateral profiling of the interface traps ( ${\Delta {\mathrm{ N}}_{\mathrm{ it}}}$ ), localized charges ( ${\Delta {\mathrm{ N}}_{\mathrm{ ot}}}$ ), and trapped holes ( ${\Delta {\mathrm{ N}}_{\mathrm{ hole}}}$ ) in P-SONOS cell devices. Charge pumping current ( ${\rm I_{\mathrm{ CP}}} $ ) measurement can be used to probe ${\Delta {\mathrm{ N}}_{\mathrm{ it}}}$ and ${\Delta {\mathrm{ N}}_{\mathrm{ ot}}} $ from the increase of maximum ${\rm I_{\mathrm{ CP}}\;({\mathrm{ I}}_{\rm CP,{\mathrm{ max}}} )}$ and the shift of ${\rm I_{\mathrm{ CP}}} $ curve along the base level voltage ( ${\rm V_{\mathrm{ b}}} $ ). When increasing the program and erase (P/E) cycles, the negative threshold voltage ( ${\rm V_{\mathrm{ T}}} $ ) shift at both program and erase states suggests the generation of ${\Delta {\mathrm{ N}}_{\mathrm{ hole}}}$ . The evolution of ${\Delta {\mathrm{ N}}_{\mathrm{ it}}} $ , ${\Delta {\mathrm{ N}}_{\mathrm{ ot}}} $ , and ${\Delta {\mathrm{ N}}_{\mathrm{ hole}}}$ during P/E cycling can consistently explain the nonmonotonic variations of gate induced drain leakage current ( ${\rm I_{\mathrm{ GIDL}}}$ ) and substrate current ( ${\rm I_{\mathrm{ SUB}}}$ ) as well as dramatic differences between the source and drain. The lateral migration of ${\Delta {\mathrm{ N}}_{\mathrm{ ot}}}$ caused by extending P/E cycles may lead to the failure of two-bit operation in SONOS cell devices. The larger ${\rm V_{\mathrm{ T}}}$ shift and subthreshold swing, smaller read current, and lower transconductance may degrade the endurance and retention of P-SONOS when applied in Flash memory.