A comprehensive analysis of LDMOS transistors for analog applications under γ-radiation

Abstract

LDMOS (laterally-diffused-metal-oxide-semiconductor) technology has been studied rigorously for high power and high voltage applications in communication systems, wireless networks, and high-frequency circuits, etc. due to its high voltage handling capability, high power density, low on-resistance, high linearity, etc. Often the device has to face radiation hazards for applications eg. space shuttles, drones, etc. Power transistors face hot carrier degradation (HCD) with total ionizing dose (TID) radiation and the overall performance of the device is degraded with radiation. Reducing or eliminating HCD from an LDMOS needs device structure modification which is often challenging and costly. There is a strong correlation between HCD and TID when coexist. It is important to study the LDMOS under radiation, especially for analog circuit performance parameters. In this work, the laterally defused LDMOS is extensively studied with a Sentaurus device simulator, for circuit application parameters such as threshold voltage (VTH), transconductance (GM), cut-off frequency (fT), output resistance (R0), and parasitic capacitances under total ionizing dose (TID) radiation. The device is also studied for low-frequency (1/f) noise under radiation. The simulation is well-calibrated with experimental results. As experimentally verified earlier, in this device TID can essentially upsurge the overall HCD-limited lifetime of an LDMOS transistor unexpectedly. In addition to better HCD behavior, the device offers better analog performance parameters and 1/f noise performances under TID radiation.