Abstract
Control-dominated devices are usually modeled as a composition of finite state machines. FSMs can be hierarchically composed to dominate the modeling complexity or can be aggregated into an interacting architecture to partition a complex behavior. A hierarchical or interacting FSM based representation can be extracted from a device's description given by means of a hardware description language. The core of the paper concerns the definition of a complete testing strategy based on the comparison between these FSMs' representations and the structural representations of the device. This comparison simplifies the testing problem by using the functional information to perform scan insertion, redundancies removal and test pattern generation considering the actual stuck-at fault model on the gate-level implementation. Therefore, a fully testable implementation can be thus obtained even for such devices which cannot be satisfactorily analyzed at the gate level.
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