A comparison of high frequency cell designs for high voltage DMOSFETs

Abstract

To reduce the conduction and switching losses in a MOSFET, it is desirable to reduce its specific on-resistance (R/sub on,sp/) and the specific input capacitance (C/sub in,sp/). In this paper, the Atomic Lattice Layout (ALL) and the Circular Layout (CL) are compared for a high frequency 400 V n-channel MOSFET with the goal of obtaining the lowest R/sub on/C/sub in/ product. The terrace gate design on ALL, with 6000 /spl Aring/ field oxide under the terrace gate region resulted in a R/sub on/C/sub in/ product of 603 /spl Omega/-pf which is nearly 4 times lower than the conventional DMOS design. It was also found to be superior to the same gate design on a CL. In the cell structure with a floating P/sup +/ diffusion, the gate-drain component (C/sub gd/) of the input capacitance (C/sub in/) was reduced by moving the floating P/sup +/ diffusion edge closer to the P-base edge at the expense of increasing the on-resistance. By studying the variation of the R/sub on/C/sub in/ product as a function of the position of the floating P/sup +/ edge, lowest R/sub on/C/sub in/ products of 452 /spl Omega/-pf and 360 /spl Omega/-pf were obtained for the ALL and CL, respectively. Although the R/sub on/C/sub in/ product of this structure is smaller than the terraced gate structures, the specific on-resistance is larger (98 m/spl Omega/-cm/sup 2/ vs 68 m/spl Omega/-cm/sup 2/ for the ALL and 137 m/spl Omega/-cm/sup 2/ vs 86 m/spl Omega/-cm/sup 2/ for the CL), which implies an increase in the die area. It was shown through simulations that the specific on-resistance did not increase appreciably with a reduction in the gate bias from 10 V to 5 V. Hence operation at 5 V gate bias is recommended to reduce the gate switching losses, which increase as the square of the gate drive voltage.