2.7 kV epitaxial lateral power DMOSFETs in 4H-SiC

Abstract

Summary form only given. SiC is attractive for power switching applications due to its high avalanche breakdown field (2-3 MV/cm) and superior chemical and thermal properties. Lateral double-implanted MOSFETs fabricated on an insulating 4H-SiC substrate have demonstrated record-high blocking voltages (Spitz et al., 1998). However, first generation LDMOSFETs used ion implants to form the p-base region, and these devices suffered from very low MOS channel mobility (/spl Lt/1 cm/sup 2//V/spl middot/s) due to the high temperature implant anneal (Das et al., 1999). In this report, we describe a new device structure that combines the high blocking voltage of the insulating substrate with the higher MOS mobility of an epitaxially-grown accumulation channel (Tan et al., 1998). Both the p-well and n-type MOS channel layer are epitaxially grown and selectively etched. No p-type implant is required. The p-well is doped at 5/spl times/10/sup 18/ cm/sup -3/ and is 0.2 /spl mu/m thick, while the n-type channel is doped at 5/spl times/10/sup 15/ cm/sup -3/ and is 0.35 /spl mu/m thick. These profiles and thicknesses are chosen so the n-type channel is completely depleted from the p-base beneath, resulting in a MOSFET threshold voltage of about 6 V at room temperature. The device exhibits a blocking voltage of 2.7 kV, with a specific on-resistance of 3.18 /spl Omega/-cm/sup 2/. At 155/spl deg/C, the threshold voltage and specific on-resistance drop to 3 V and 1.85 /spl Omega//spl middot/cm/sup 2/ respectively. The figure of merit V/sub block//sup 2//R/sub on/ for this device is approximately equal to the theoretical limit for Si power MOSFETs, and the specific on-resistance is the lowest reported to date for any power MOSFET in this voltage range.